View 840S06AKILF_4532773.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY
CLOCK GENERATOR FOR CAVIUM PROCESSORS
ICS840S06I
General Description
The ICS840S06I is a PLL-based clock generator specifically designed for Cavium Networks SoC HiPerClockSTM processors. This high performance device is optimized to generate the processor core reference clock, the DDR reference clocks, the PCI/PCI-X bus clocks, and the clocks for both the Gigabit Ethernet MAC and PHY. The clock generator offers ultra low-jitter, low-skew clock outputs, and edge rates that easily meet the input requirements for the OCTEON processors. The output frequencies are generated from a 25MHz external input source or an external 25MHz parallel resonant crystal. The extended temperature range of the ICS840S06I supports telecommunication, networking, and storage requirements.
Features
*
Six LVCMOS/ LVTTL outputs, 20 typical output impedance - One selectable core clock for the processor - One selectable clock for the PCI/ PCI-X bus - One 125MHz clock reference for GbE MAC - Three 25MHz clock references for GbE PHY Selectable external crystal or differential (single-ended) input source Crystal oscillator interface designed for 25MHz, parallel resonant crystal Differential input pair (CLK, nCLK) accepts LVPECL, LVDS, LVHSTL, SSTL, HCSL input levels Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels Full 3.3V or mixed 3.3V core/2.5V output supply mode -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) packages
ICS
* * * * * * *
Applications
* *
Systems using OCTEON MIPS64 Broadband Processors Networking, control and storage equipment, including routers, switches, application-aware gateways, triple-play gateways, WLAN and 3G/4G access and aggregation devices, storage arrays, storage networking equipment, servers, and intelligent NICs 802.11 a/b/g/n wireless for home data and multimedia distribution QoS for high quality Voice, Video, and Data service Next-generationPON, VDSL2, and Cable networks High-performance NAS Audio/Video Storage and distribution Consumer space media server
VDD nPLL_SEL XTAL_IN 1 2 3
* * * * * *
Pin Assignment
VDDO_REF QREF0 QREF1 QREF2 VDDO_REF GND QC VDDO_C
32 31 30 29 28 27 26 25 24 VDDO_B QB
ICS840S06I ICS8430S07I 32-Lead VFQFN 32-Lead VFQFN 5mm x 5mm x 0.75mm 5mm x 5mm x 0.75mm package body Package body K Package K Package Top View Top View
9 10 11 12 13 14 15 16
23 22 21 20 19 18 17
CORE_SEL
GND GND nOE_REF
XTAL_OUT 4 nXTAL_SEL CLK nCLK GND 5 6 7 8
QA
VDDO_A
PCI_SEL1
PCI_SEL0
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDTTM / ICSTM CLOCK GENERATOR
1
ICS840S06AKI REV. AI JULY 10, 2008
VDDA
VDD
nc
nc
nc
nc
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Block Diagram
nPLL_SEL nXTAL_SEL
XTAL_IN
25 MHz XTAL
XTAL_OUT
OSC
0 1
PLL
0 = 50.000 MHz 1 = 33.333 MHz
QA
Processor Core Clock (LVCMOS)
0 1
00 = 133.333 MHz 01 = 100.000 MHz 10 = 66.667 MHz 11 = 33.333 MHz 125 MHz GbE CLK
25 MHz
CLK nCLK
QB
PCI or PCI-X Clock (LVCMOS) Gigabit Ethernet MAC Clock (LVCMOS)
QC
CORE_SEL QREF0 PCI_SEL1:0 nOE_REF Clock Output Control Logic
25 MHz GbE CLK \ \ Gigabit Ethernet QREF1 / PHY Clocks / (LVCMOS) QREF2
IDTTM / ICSTM CLOCK GENERATOR
2
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Table 1. Pin Descriptions
Number 1, 15 2 3, 4 5 6 7 8, 20, 21, 27 9, 10 11, 12, 13, 14 16 17 18, 23, 26, 29, 30, 31 Name VDD nPLL_SEL XTAL_IN, XTAL_OUT nXTAL_SEL CLK nCLK GND PCI_SEL1, PCI_SEL0 nc VDDA VDDO_A QA, QB, QC, QREF2, QREF1, QREF0 nOE_REF Power Input Input Input Input Input Power Input Unused Power Power Output Pulldown Pulldown Pulldown Pullup/ Pulldown Pulldown Type Description Core supply pins. PLL bypass. When LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. Selects XTAL inputs when LOW. Selects differential clock (CLK, nCLK) input when HIGH. LVCMOS/LVTTL interface levels. Non-inverting differential clock input. Inverting differential clock input. Internal resistor bias to VDD/2. Power supply ground. Selects the PCI/PCI-X reference clock output frequency. See Table 3B. LVCMOS/LVTTL interface levels. No connect. Analog supply pin. Bank A output supply pin. 3.3 V or 2.5V supply. Single-ended outputs. LVCMOS/LVTTL interface levels. Active LOW output enable. When logic HIGH, the outputs are in high impedance (HI-Z). When logic LOW, the outputs are enabled. LVCMOS/ LVTTL interface levels. Selects the processor core clock output frequency. The output frequency is 50MHz when LOW, and 33.333MHz when HIGH. See Table 3A. LVCMOS/LVTTL interface levels. Bank B output supply pin. 3.3 V or 2.5V supply. Bank C output supply pin. 3.3 V or 2.5V supply. REF bank output supply pins. 3.3 V or 2.5V supply.
19
Input
Pulldown
22 24 25 28, 32
CORE_SEL VDDO_B VDDO_C VDDO_REF
Input Power Power Power
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDTTM / ICSTM CLOCK GENERATOR
3
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Table 2. Pin Characteristics
Symbol CIN CPD RPULLUP Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor VDD, VDDO_X = 3.465V VDD = 3.465V, VDDO_X = 2.625V Test Conditions Minimum Typical 4 TBD TBD 51 51 VDDO_X = 3.465V VDDO_X = 2.625V 20 25 Maximum Units pF pF pF k k
RPULLDOWN Input Pulldown Resistor QA, QB, QC, QREF[0:2] QA, QB, QC, QREF[0:2]

ROUT
Output Impedance
NOTE: VDDO_X denotes VDDO_B, VDDO_C, VDDO_D and VDDO_REF.
Function Tables
Table 3A. Control Input Function Table
Input CORE_SEL 0 1 Output Frequency QA 50MHz 33.333MHz
Table 3B. Control Input Function Table
Inputs PCI_SEL1 0 0 1 1 PCI_SEL0 0 1 0 1 Output Frequency QB 133.333MHz 100.000MHz 66.6667MHz 33.333MHz
IDTTM / ICSTM CLOCK GENERATOR
4
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, VO (LVCMOS) Outputs, IO (LVPECL) Continuos Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V -0.5V to VDD + 0.5V 50mA 100mA 39.5C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO_X = 3.3V 5%, TA = -40C to 85C
Symbol VDD VDDA VDDO_X IDD IDDA IDDO_X Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 VDD - 0.16 3.135 Typical 3.3 3.3 3.3 140 16 20 Maximum 3.465 VDD 3.465 Units V V V mA mA mA
NOTE: VDDO_X denotes VDDO_B, VDDO_C, VDDO_D and VDDO_REF.
Table 4B. Power Supply DC Characteristics, VDD = 3.3V 5%, VDDO_X = 2.5V 5%, TA = -40C to 85C
Symbol VDD VDDA VDDO_X IDD IDDA IDDO_X Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 VDD - 0.16 2.375 Typical 3.3 3.3 2.5 130 16 16 Maximum 3.465 VDD 2.625 Units V V V mA mA mA
NOTE: VDDO_X denotes VDDO_B, VDDO_C, VDDO_D and VDDO_REF.
IDTTM / ICSTM CLOCK GENERATOR
5
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, VDDO_X = 3.3V 5% or 2.5V 5%, TA = -40C to 85C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage nPLL_SEL, CORE_SEL, nXTAL_SEL, PCI_SEL[0:1], nOE_REF nPLL_SEL, CORE_SEL, nXTAL_SEL, PCI_SEL[0:1], nOE_REF Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 Units V V
IIH
Input High Current
VDD = VIN = 3.465V
150
A
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
-10
A
VOH VOL
Output High Voltage; NOTE 1 Output Low Voltage: NOTE 1
VDDO_X = 3.465V VDDO_X = 2.625V VDDO_X = 3.465V or 2.625V
2.6 1.8 0.5
V V V
NOTE 1: Outputs terminated with 50 to VDDO_X/2. See Parameter Measurement Information, Output Load Test Circuit diagram.
Table 4C. Differential DC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C
Symbol IIH IIL VPP VCMR Parameter Input High Current Input Low Current nCLK Peak-to-Peak Input Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1, 2 CLK/nCLK CLK Test Conditions VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -10 -150 0.15 0.5 1.3 VDD - 0.85 Minimum Typical Maximum 150 Units A A A V V
NOTE 1: VIL should not be less than -0.3V. NOTE 2. Common mode voltage is defined as VIH.
Table 5. Crystal Characteristics
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level Test Conditions Minimum Typical Fundamental 25 50 7 300 MHz Maximum Units
pF W
NOTE: Characterized using an 18pF parallel resonant crystal.
IDTTM / ICSTM CLOCK GENERATOR
6
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = 3.3V 5%, VDDO_X = 3.3V 5% or 2.5V 5%, TA = -40C to 85C
Parameter Symbol QA QA QB fMAX Output Frequency QB QB QB QC QREF[0:2] tsk(b) tsk(pp) tjit(cc) tjit(O) tR / tF odc Bank Skew; NOTE 2, 4 Part-to-Part Skew; NOTE 3, 4 Cycle-to-Cycle Jitter RMS Phase Jitter, (Random); NOTE 1 Output Rise/Fall Time Output Duty Cycle QREF[0:2] QREF[0:2] QA, QB, QC QREF[0:2] QC QA, QB, QC, QREF[0:2] QA, QB, QC, QREF[0:2] 25MHz (10kHz to 5MHz) 125MHz (1.875MHz to 20MHz) 20% to 80% 40 60 100 0.73 0.78 0.80 60 Test Conditions CORE_SEL = 0 CORE_SEL = 1 PCI_SEL[1:0] = 00 PCI_SEL[1:0] = 01 PCI_SEL[1:0] = 10 PCI_SEL[1:0] = 11 Minimum Typical 50 33.333 133.333 100 66.667 33.333 125 25 400 Maximum Units MHz MHz MHz MHz MHz MHz MHz MHz ps ps ps ps ps ps ns %
All parameters measured at fMAX unless noted otherwise. NOTE 1: Refer to the phase noise plot. NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDTTM / ICSTM CLOCK GENERATOR
7
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Parameter Measurement Information
1.65V5% 1.65V5% 2.05V5% 1.25V5% 2.05V5% VDD, VDDO_X VDDA
SCOPE
VDD
SCOPE
VDDO_X VDDA
Qx
LVCMOS
GND
Qx
LVCMOS
GND
-1.65V5%
-
-1.25V5%
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
VDD
Par t 1
nCLK
V
PP
V
DDOX
Qx
Cross Points V
2
CMR
CLK Qy GND
Par t 2
V
DDOX
2 tsk(pp)
Differential Input Level
LVCMOS Part-to-Part Skew
Phase Noise Plot Noise Power
80%
Phase Noise Mask
QA:QC, QREF[0:2]
80% 20%
20% tR tF
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS Phase Jitter
Output Rise/Fall Time
IDTTM / ICSTM CLOCK GENERATOR
8
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Parameter Measurement Information, continued
QREF[0:2]
VDDOX 2
QA:QC, QREF[0:2]
V
DDOX
V
DDOX
V
DDOX
2 tcycle n
2
2 tcycle n+1
QREF[0:2]
tsk(b)
tjit(cc) = |tcycle n - tcycle n+1| 1000 Cycles
Bank Skew
Cycle-to-Cycle Jitter
V
QA:QC, QREF[0:2]
DDOX
2
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
Output Duty Cycle/Pulse Width/Period
IDTTM / ICSTM CLOCK GENERATOR
9
ICS840S06AKI REV. AI JULY 10, 2008
VDDOX 2
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Application Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how the differential input can be wired to accept single-ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK
V_REF nCLK C1 0.1u
R2 1K
Figure 1. Single-Ended Signal Driving Differential Input
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS840S06I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO_X should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin.
3.3V VDD .01F VDDA .01F 10F 10
Figure 2. Power Supply Filtering
IDTTM / ICSTM CLOCK GENERATOR
10
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Recommendations for Unused Input and Output Pins
Inputs: CLK/nCLK Inputs
For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground.
Outputs: LVCMOS Outputs
All unused LVCMOS outputs can be left floating We recommend that there is no trace attached.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
IDTTM / ICSTM CLOCK GENERATOR
11
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V 1.8V Zo = 50 Zo = 50 CLK Zo = 50 Zo = 50 nCLK nCLK CLK 3.3V
LVPECL HiPerClockS Input
R1 50 R2 50
HiPerClockS Input
LVHSTL IDT HiPerClockS LVHSTL Driver
R1 50 R2 50
R2 50
Figure 3A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver
3.3V 3.3V 3.3V R3 125 Zo = 50 CLK CLK Zo = 50 nCLK R1 100 R4 125 3.3V 3.3V Zo = 50
LVPECL
R1 84 R2 84
HiPerClockS Input
Zo = 50
nCLK
LVDS
Receiver
Figure 3C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver
2.5V 3.3V 2.5V R3 120 Zo = 60 R4 120
2.5V
3.3V
*R3
33
Zo = 50 CLK Zo = 50 nCLK Zo = 60
CLK
nCLK
HCSL
*R4
33 R1 50 R2 50
HiPerClockS Input
SSTL
R1 120 R2 120
HiPerClockS
*Optional - R3 and R4 can be 0
Figure 3E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver
Figure 3F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver
IDTTM / ICSTM CLOCK GENERATOR
12
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Crystal Input Interface
The ICS840S06I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 4 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_IN C1 22p(TBD) X1 18pF Parallel Crystal XTAL_OUT C2 22p(TBD)
Figure 4. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 5. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
VDD
R1 Ro Rs 50 0.1f XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 5. General Diagram for LVCMOS Driver to XTAL Input Interface
IDTTM / ICSTM CLOCK GENERATOR
13
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 6. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology.
PIN
SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
IDTTM / ICSTM CLOCK GENERATOR
14
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS840S06I. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS840S06I is the sum of the core power, analog power, and power dissipated in the load. The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core Output Power Dissipation * Power (core)_MAX = VDD_MAX * (IEE_MAX + IDDA + IDDO) = 3.465V * (140mA + 16mA + 20mA) = 609.84mW Output Impedance ROUT Power Dissipation due to Loading 50 to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 20)] = 24.8mA * Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 20 * (24.8mA)2 = 12.3mW per output * Total Power Dissipation on the ROUT
LVCMOS Output Power Dissipation *
Total Power (ROUT) = 12.3mW * 6 = 73.8mW
* Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * Frequency * (VDDO)2 = 10pF * 25MHz * (3.465V)2 = 3mW per output
Total Power (25MHz) = 3mW * 3 = 9mW
*
Dynamic Power Dissipation at 133MHz Power (133MHz) = CPD * Frequency * (VDDO)2 = 10pF * 133MHz * (3.465V)2 = 16mW per output
Total Power (133MHz) = 16mW * 3 = 48mW
Total Power Dissipation * Total Power = Power (core) + Total Power (ROUT) + Total Power (25MHz) + Total Power (133MHz) = 610mW + 73.8mW + 9mW + 48mW = 741mW
IDTTM / ICSTM CLOCK GENERATOR
15
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 39.5C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.741W * 39.5C/W = 114C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer).
Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
JA Vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 39.5C/W 1 34.5C/W 2.5 31.0C/W
IDTTM / ICSTM CLOCK GENERATOR
16
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Reliability Information
Table 8. JA vs. Air Flow Table for a 32 Lead VFQFN
JA Vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 39.5C/W 1 34.5C/W 2.5 31.0C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS840S06I is: 10,871
IDTTM / ICSTM CLOCK GENERATOR
17
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
S eating Plan e Ind ex Area N Anvil Singula tion A1 A3 L N 1 2 E2 (N -1)x e
E2 2
(Re f.) (Ref.)
(N -1)x e
(R ef.)
N &N Even
e (Ty p.) 2 If N & N
are Even
OR
To p View
b A D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C
(Ref.)
e D2 2 D2
N &N Odd
Th er mal Ba se
The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9 below.
Table 9. Package Dimensions
JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220
IDTTM / ICSTM CLOCK GENERATOR
18
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Ordering Information
Table 10. Ordering Information
Part/Order Number 840S06AKILF 840S06AKILFT Marking ICS40S06AIL ICS40S06AIL Package "Lead-Free" 32 Lead VFQFN "Lead-Free" 32 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Temperature -40C to 85C -40C to 85C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDTTM / ICSTM CLOCK GENERATOR
19
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Contact Information:
www.IDT.com
Sales
800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT
Technical Support
netcom@idt.com +480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA)
www.IDT.com
(c) 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

▲Up To Search▲

Price & Availability of 840S06AKILF

	To Download 840S06AKILF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .